Example embodiments relate generally to semiconductor integrated circuits, and more particularly to a command processing circuit, a memory device and a memory system including the command processing circuit.
A memory device is generally equipped to receive a command signal from a host device such as a memory controller. Standards associated with the memory device define a clock timing according to which the memory device receives the command signal. That is, the memory device is configured to receive the command signal at each clock in order to decode and process the command signal within a clock cycle.
As techniques for manufacturing memory devices evolve to allow for higher operating speeds, it has become increasingly difficult to process the command signal within each clock cycle. In an effort to overcome this problem, a plurality of processing units may be included in the memory device to allow for processing of the command signal using a time-interleaved scheme. However, time-interleaved processing using multiple command processing units suffers the drawback of increased power consumption.